1. Field of the Invention
The present invention relates to a layout design method on a semiconductor chip for avoiding detour wiring and a semiconductor device produced with applying the same.
2. Description of the Related Art
FIG. 10 is a schematic block diagram of ASIC in which macro cells 11 to 14 with the same configuration to each other are arranged on a semiconductor chip according to a user""s request.
A macro cell 11 is an SRAM, as shown in FIG.11, comprising a memory circuit 20 and a defect-repairing control circuit 30. The memory circuit 20 is provided with a switching circuit 201, memory blocks 2-1 to 2-36 and a redundant memory block 2-37. The memory blocks 2-1 to 2-37 have the same configuration to each other and a capacity of each block is, for example, 4 k bit.
A read/write test is performed on the memory circuit 20 prior to shipment of a semiconductor chip 10 and, for example, when it is detected that a memory cell indicated by an X mark in the memory block 2-2 is defective, the memory blocks 2-1 and 2-3 to 2-37 are in use, excluding the memory block 2-2. That is, wiring of data input/output ends of memory blocks are shifted in units of a block by a switching circuits 201, so that the memory blocks 2-1 and 2-3 to 2-37 go into use, instead of the memory blocks 2-1 to 2-36.
The defect-repairing control circuit 30 comprises circuits 31 to 34 in order that the defect-repairing control circuit 30 provides switching signals to the switching circuit 201 depending on a location of a defective memory block and makes the switching circuit 201 perform connection switching.
A location of a defective memory block is designated by cutting off a fuse in a fuse circuit 31 by irradiating it with laser beam. Since a fuse is relatively large in size, coded outputs of the fuse circuit 31 are used in order to decrease the number of fuses. The outputs are decoded in a predecoder 32 and a main decoder 33 and outputs of a signal conversion circuit 34 are provided to the switching circuit 201.
Since wiring cannot be laid in an upper layer of the fuse circuit 31, when wiring of signal and power is designed on a user side, as shown in FIG. 12, wiring has to be laid with making a detour around the defect-repairing control circuit 30 whose majority area is the fuse circuit. Hence, there arise problems that not only an area for the wiring increases due to increase in length of the wiring, but also a signal propagation delay time becomes longer. These problems also arise in the case where a different element, instead of a fuse, whose upper layer wiring is prohibited is used.
Accordingly, it is an object according to the present invention to provide a layout design method on a semiconductor chip in which detour wiring can be reduced or absent, and a semiconductor device produced with applying the same.
In the present invention, there is provided a semiconductor device wherein an element over which wiring is prohibited to be laid is arranged in a peripheral area of a semiconductor chip or a functional block on the semiconductor chip.
With the present invention, detour wiring around the element over which wiring is prohibited is reduced or absent and thereby, not only an area for the wiring can be reduced due to suppression of increase in length of wiring but a signal propagation delay time can also be shortened.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.